1. Field of the Invention
The present invention relates to a semiconductor memory circuit, particularly to a semiconductor memory circuit in which data for one word can be written in a corresponding amount of memory cells in one access activity.
2. Description of the Related Art
Hitherto, in semiconductor memory circuits of this type, a flash write gate (hereinafter referred to as an FW gate) has been activated or inactivated in synchronization with a trailing edge or leading edge of a row address strobe (hereinafter referred to as RAS, where the sign .sup.-- shows that signals or terminals are active when they are at a low logic level), thereby performing an FW function of the semiconductor memory circuit. (For example, reference may be made to Japanese Patent Laid-open No. 29987/90.)
The structure and operation of an example of a semiconductor memory circuit of the conventional type will be described with reference to FIGS. 1 to 4. FIG. 1 is a block diagram showing the structure of an example of the conventional type, and FIG. 2 is a circuit diagram showing a principal part of the diagram of FIG. 1. In FIG. 1, a row address decoder 308 is connected on one side to a memory cell array 306 through word lines 309 (WL1, WL2, . . . ), and on the other side to a row address buffer 307. Address data are supplied to the row address buffer 307 through address pins A1 to An. Also, to the bit lines on the column side of the memory cell array 306, there are connected a sense amplifier 310 (SA1, SA2, . . . in FIG. 2), a column switch 301 (Q1, Q1', Q2, Q2', . . . in FIG. 2), and an FW gate 304 (SW1, SW2, . . . in FIG. 2). A column address buffer 313 is connected to a column address decoder 311, which is in turn connected to the column switch 301. Address data are inputted to the column address buffer 313 through the address pins A1 to An.
Further, the column switch 301 is connected through input/output buses 302, 303 to a data latch circuit 314, which is in turn connected to an input/output terminal 317 (hereinafter referred to as an I/O terminal 317). The FW gate 304 is connected to the data latch circuit 314 through a flash write data bus 305 (hereinafter referred to as an FW data bus 305). The FW gate 304, row address buffer 307, row address decoder 308, sense amplifier 310, row address decoder 311, column address buffer 313 and data latch circuit 314 are controlled by various signals that are inputted to a controller 315. These inputted signals include an RAS signal, a column address strobe signal (hereinafter referred to as a CAS signal), a write enable signal (hereinafter referred to as a WE signal), and a flash write enable signal (hereinafter referred to as an FWE signal).
In addition to the input/output buses 302, 303, the conventional semiconductor memory circuit has an FW gate 304 and FW data bus 305, which are exclusively used for flash writing. The input/output buses are usually composed of a pair of buses including bus 302 which carries write (or read) data (hereinafter referred to as I/O bus 302) and bus 303 which carries data of an opposite phase (hereinafter referred to as I/O bus 303). However, the FW data bus 305 can be structured with only one line which carries data of a positive phase (or a negative phase). FIG. 2 shows a principal part of a concrete example of a circuit of the conventional semiconductor memory circuit which employs an FW data bus consisting of only one line.
The following description is made with reference to bit lines D1 and D1 of FIG. 2. Specifically, a memory cell MC1 is connected to a bit line D1 and a word line WL1 where the two lines cross, and a memory cell MC2 is similarly connected to a bit line D1 and a word line WL2. The pair of bit lines D1, D1 are further connected to a sense amplifier SA1. The bit lines D1 and D1 are also connected to I/O bus 302 and I/O bus 303 through switches Q.sub.1, Q.sub.1 ', respectively, both switches being N-type MOS transistors. Furthermore, bit line D1 is connected to the FW data bus 305 through a flash write switch SW1 (an N-type MOS transistor, hereinafter referred to as FW switch SW1) of the FW gate 304. Switches Q.sub.1, Q.sub.1 ' are controlled by a signal YSW1 outputted from the column address decoder 311, and FW switch SW1 is controlled by FW gate signal 318. In this case, although FW data of a positive phase (high level) are transmitted to the FW data bus 305 and FW switch SW1 is connected to bit line D1, positive FW data may also be low level. Specifically, FW data may also be transmitted at a low level to the FW data bus 305 while connecting the FW switches (SW1, SW2, . . . ) to the bit lines (D1, D1, . . . ).
The operation of the conventional semiconductor memory circuit illustrated in FIG. 1 and FIG. 2 will next be described with reference to the timing charts of FIG. 3 and FIG. 4. When operating in a flash write mode (hereinafter referred to as FW mode), as shown in FIG. 3, an FWE signal is first activated (high level) followed by activation of an RAS signal (low level). When the RAS signal is activated, a row address corresponding to a word line activated for flash writing is stored in the row address buffer 307 (FIG. 1) and then decoded by the row address decoder 308. As a result of decoding, word line WL1 for example (one of word lines 309 which include word lines WL1, WL2, . . . ) is turned to high level, and thus the data is stored in memory cell MC1, for example the data "0," is fetched on bit lines D1, D1. It is to be noted that, by this time, FW data of positive phase has already been transmitted from the data latch circuit 314 to the FW data bus 305 as a result of the activation of the FWE signal.
The controller 315 then activates (high level) an FW gate signal 318 to operate FW switch SW1 for outputting FW data to bit line D1, for example, FW data "0" fetched from the I/O terminal 317 to the data latch circuit 314. With this outputted FW data, bit line D1 is compulsorily driven toward the direction of "0," and when the controller 315 activates a sense amplifier activation signal, a signal SEP for supplying a signal of a +Vcc level and a signal SEN for supplying a signal of a ground level are activated to further activate sense amplifier SA1, thereby causing sense amplifier SA1 to amplify the FW data on the bit line. As a result of this amplification, bit line D1 turns to "0," bit line D1 turns to "1," and "1" is also stored in memory cell MC1 connected to bit line D1. In the same way as described above, FW data are also stored in the same cycle in other memory cells connected to word line WL1.
In the case of normal reading, as shown in FIG. 4, a word line with a predetermined row address, e.g., WL1, is activated due to activation of an RAS signal to output the data of memory cell MC1, e.g., "1," to the bit line. Subsequently, when sense amplifier SA1 is activated by the sense amplifier activating signals SEP and SEN, and the data of memory cell MC1 are amplified, column switches Q.sub.1, Q.sub.1 ' are turned on for fetching the data of the pair of bit lines D1, D1 to the I/O buses 302, 303. In the case of writing, in contrast to the above, the data on the I/O buses 302, 303 are transmitted to the pair of bit lines D1, D1 by turning the column switches Q.sub.1, Q.sub.1 ' on.
To simplify the FW gate activation circuit, as shown in the timing chart of FIG. 3, the conventional semiconductor memory circuit is structured such that FW gate signals are activated or inactivated in synchronization with the activation or inactivation of an RAS signal, respectively. The longer the activation period of the RAS signal, the longer the activation period of the FW gate signal.
In the conventional semiconductor memory circuit, if a bit line is short-circuited by, for example, a signal SEP line or a word line due to problems in the manufacturing process (for example, if a transistor Tr of sense amplifier SA1 in FIG. 2 is activated while a resistance between P1 and N1 is much lower than standard), the quality of the semiconductor memory circuit will be impaired. However, if the circuit is provided with redundant bit lines and a circuit related therewith which can substitute for the portion relating to the defective bit lines, the quality of the semiconductor memory circuit can be restored by replacing the defective lines with the redundant lines.
However, if the FW switch is connected to the defective bit line, the FW switch becomes active in the FW mode and the FW data are transmitted to the defective bit line through the FW data bus 305. In this case, if the defective bit line has a voltage by which the polarity of data of the defective line becomes the reverse of that of the FW data, for example, if the voltage of the FW data is "0" and the defective bit line is short-circuited by a line having a voltage Vcc or by a word line, an electric current flows from the line having the voltage Vcc or from the word line to the FW data bus, thereby causing the operation current to disadvantageously increase in the FW mode.